1. Field of the Invention
This invention relates to a memory access control system. and more particularly to a memory access control system which employs a shift register storing address information of a memory unit (hereinafter referred to as a logical storage) in its busy state, and is capable of controlling the reception of a request for access with a simple construction, even in the case where the number of independently accessible logical storages is increased.
2. Description of the Prior Art
In such a multiprocessor system in which, for example, a large capacity storage is shared by a plurality of accessing devices (that is, central processing units and/or channel processors) to increase the throughput by multiple processing of requests from the accessing devices, the wait times of the accessing devices are shortened by forming the large capacity storage with a plurality of independently accessible logical storages and increasing the number of logical storages. There has been known in the art a memory access control system of the type in which flip-flops are provided to have one to one correspondence to the logical storages, and the status of each logical storage is checked based on the content of each flip-flop and receives the request for access when the logical storage requested to be accessed is idle. In this type of memory access control system, however, it is necessary to increase the number of flip-flops with an increase in the number of logical storages. Accordingly, where a relatively large number of logical storages are provided, the overall control system becomes bulky.